The present invention relates to configurations for providing robust electrostatic discharge (ESD) protection for high voltage semiconductor devices.
In high voltage semiconductor circuits, protection from damage due to ESD events is important. ESD protection circuits are generally known for this purpose. However, in some circuits, conventional ESD protection circuits may not be sufficient to protect the semiconductor devices in the circuits from damage. For example, in some situations it is difficult to provide sufficient ESD protection in a circuit configuration where a metal oxide semiconductor (MOS) device, such as a doubly diffused MOS (DMOS) device, is placed in parallel with an ESD clamp device. When the DMOS drain and the ESD clamp cathode are both positive (for example, placed across a supply voltage and ground), the gate of the DMOS device can be pulled high, turning the device on, and the DMOS device can “snap-back” (enter a mode of operation in which large amounts of current are conducted with a reduced voltage) and incur destruction at a voltage significantly lower than the rated breakdown value of the DMOS device and the ESD clamp turn-on voltage.
It would be useful to provide a circuit configuration to hold down or pull down the gate of the DMOS device during an ESD pulse, to turn the device off and increase its snap-back voltage to be nearer to the rated breakdown voltage of the device.